Thinned, back illuminated, semiconductor imaging devices are advantageous over front-illuminated imagers for high fill factor and better overall efficiency of charge carrier generation and collection. A goal of the operation of such devices is for the charge carriers generated by light or other emanation incident on the backside to be driven to the frontside quickly to avoid any horizontal drift which may smear the image. It is also desirable to minimize the recombination of the generated carriers before they reach the front side, since such recombination reduces overall efficiency and sensitivity of the device.
Such desirable features may be achieved by providing a thin semiconductor layer and a high electric field within this layer. The field should extend to the back surface, so that the generated carriers, such as electrons or holes, can be driven quickly to the front side. U.S. Pat. No. 7,238,583 by Swain et. al. (the “'583 patent”), which is incorporated herein by reference in its entirety, describes a method for producing a back-illuminated imaging device that exhibits the desired internal electric field. The device of the '583 patent also employs ultra-thin Silicon-on-Insulator (UTSOI) technology for providing a semiconductor substrate on which the back-illuminated imager is constructed. The practical work flow for using the method of described in the '583 patent in production is shown in FIG. 1.
In FIG. 1, the starting structure is an initial substrate 10, sometimes referred to in the art as a UTSOI substrate. The starting UTSOI substrate 10 is composed of a mechanical substrate 12 (handle wafer) configured to provide mechanical support during processing, an insulator layer 14 (which can be, for example, a buried oxide layer of silicon (BOX)), and a semiconductor substrate 16 (also referred to as the “seed layer”). In Step A, the UTSOI wafer 10 is cleaned and then an oxide layer 18 is grown overlying the seed layer 16 opposite the mechanical substrate 12. In Step B, the seed layer 16 is doped. Dopants are introduced into the seed layer 16 in sufficient concentration to produce a desired net doping profile. The initial net doping concentration in the seed layer 16 may be on the order of 1017 charge carriers per cubic centimeter or higher, and may be either p-type or n-type. Common dopants include boron, phosphorous, antimony, and arsenic.
In the specific case where the semiconductor is silicon, the '583 patent cites boron as the most suitable dopant for producing p-type regions. In this example, the boron dopant is incorporated within the semiconductor before the growth of the epitaxial layer. Although the '583 patent outlines several techniques for introducing the boron dopant, the preferred method for introduction of p-type dopants is through the use of ion-implantation. With reference to this example, in Step B, ions of boron are implanted ballistically through the oxide layer 18 into the seed layer 16 of UTSOI wafer 10.
In Step C, the UTSOI wafer 10 is cleaned and annealed in a furnace to remove the damage introduced by the ion implantation of dopants, i.e., broken bonds are reformed and dopants are incorporated at lattice sites. In Step D, the oxide layer 18 is removed and the resulting doped wafer 10′ is cleaned. In Step E, an epitaxial layer 20 is grown overlying doped semiconductor substrate 16, using semiconductor substrate 16 as the template. The epitaxial layer 20 provides a layer for fabricating front side components which complete the overall imaging device. Still referring to FIG. 1, during the growth of epitaxial layer 20, dopants previously introduced into the seed layer 16 diffuse into the epitaxial layer 20 as a result of processing at or above 1000° C. At the conclusion of the growth of the epitaxial layer 20, the net doping profile is very close to the desired profile, in that at each distance from interface 22 between the insulator layer 14 and the seed layer 16, within the seed layer 16 and epitaxial layer 20, the net carrier concentration is close to its final desired value, as shown in FIG. 1B. All remaining steps in the process are then carried out at lower temperatures, so that relatively little diffusion of dopants takes place, and the profile is essentially unchanged at the end of the process.
In Step F, once the epitaxial layer 20 is grown, with the simultaneous formation of a desired dopant profile, one or more imaging components 24 may be fabricated using known methods of semiconductor fabrication, as shown in FIG. 1. These imaging components may include charge-coupled device (CCD) components, CMOS imaging components, photodiodes, avalanche photodiodes, phototransistors, or other optoelectronic devices, in any combination. Components 24 may include both CCD and CMOS components fabricated in separate areas of the epitaxial layer 20 using known masking methods. Also included may be other electronic components such as CMOS transistors, (not shown) bipolar transistors (not shown), capacitors (not shown), or resistors (not shown). One or more p-n junctions 26 of various depths may be formed during the fabrication of imaging components 24.
In Step G, the mechanical substrate 12 is removed. Once the fabrication of components 24 is complete, the mechanical substrate 12 is no longer needed to provide mechanical stability. Removal of the mechanical substrate 12 may also be desirable in order to allow the emanation being detected to reach the backside semiconductor. Removal of the mechanical substrate 12 may be accomplished by such methods as chemical etching, mechanical grinding, or a combination of these methods. With chemical etching, the mechanical substrate 12 may be removed selectively, without removing the insulator layer 14. Alternatively, at least a portion of the mechanical substrate 12 may be left in place (not removed) if the remaining portion at least partially transmits the radiation or particles being detected and imaged.
If the mechanical substrate 12 is entirely removed, the insulator layer 14 may be removed, either partially or entirely, by chemical or physical methods or a combination of the two methods. In one embodiment, the insulator layer 14 is made to act as an anti-reflection coating for electromagnetic waves having wavelengths in a predetermined range, thereby allowing more photons to reach, and be absorbed in, the semiconductor layers 16, 20. This may be accomplished by reducing thickness of the insulator layer 14 to a thickness which minimizes reflection in the predetermined wavelength range. The thickness may be determined by the wavelength range and the index of refraction of the material of the insulator layer 14 in this wavelength range.
After partially removing the insulator layer 14, one or more anti-reflective coating layers (e.g., zirconium oxide or bismuth oxide) (not shown) can be deposited on the insulation layer 14 to function as an overall anti-reflective coating stack for a desired range of wavelengths. In still other embodiments, the insulation layer 14 can be completely etched away, and one or more anti-reflective coating layers can be deposited on the seed layer 16 so as to function as an overall antireflective coating.
FIG. 2 shows a complete laminated imaging device 28 as described in the '583 patent, with an anti-reflection coating 30. For thin devices, a sufficiently rigid lamination layer 32 may be added to provide mechanical stability. In FIG. 2 the lamination layer 32 is shown on the front side of the imaging device 28. Lamination layer 32 may be bonded to the front side of the wafer with cement after concluding the fabrication of imaging components 24 and other front-side components. Alternatively, the lamination layer may be bonded to the back of the imaging device 28. If the lamination layer 32 is bonded to the back of the imaging device 28, lamination layer material, any cement used to bond the lamination layer, and any other materials between the lamination layer 32 and the back of the imaging device 28 must be transparent to, and not degraded by, detected radiation.
Referring again to FIG. 1, a goal of the process for manufacturing a back-illuminated imaging device described in the '583 patent is the creation of a final net dopant concentration profile in semiconductor substrate 16 and epitaxial layer 20 which has a maximum value at the interface 22 between semiconductor substrate 16 and insulator layer 14. The final net dopant concentration profile after the epitaxial growth (i.e., Step E) decreases monotonically with increasing distance from the interface 22 within a portion of semiconductor substrate 16 and epitaxial layer 20 between interface 22 and p-n junctions 26 shown in FIG. 1 (p-n junctions 26 are created during fabrication of the front-side components 24). Such a profile may give rise to an electric field within semiconductor substrate 16 and epitaxial layer 20 tending to drive photo-generated electrons toward the front side imaging components 24 and minimizing the trapping of these electrons near the backside.
One of the concerns expressed about high-resolution imaging devices made using technology that is similar to that disclosed in the '583 patent is that boron doping diffuses too far from the seed layer 16 into and through the lightly doped epitaxial layer 20 before and during the fabrication of the imaging components 24. Although the resulting device produces a desired monotonically decreasing doping profile in the seed layer 16 and the epitaxial layer 20, the resulting profile may have a slope that is too gradual, resulting in reduced performance of the imager With regard to light sensitivity and spatial resolution. There are cases where a more abrupt transition from heavy doping to uniform doping is an advantage.
Accordingly, what would be desirable, but has not yet been provided, is a method and resulting device for producing imagers that exhibit a more abrupt doping profile as compared to prior art devices.